Memory cells within integrated circuits (ICs) are continually shrinking in order to achieve increased packing density and future generations of memory ICs. In order to achieve increased packing density, several transistors must be formed within an increasingly smaller area. Several transistors are formed into a smaller surface area by combining functionality (i.e. sharing gates, double gating, sharing source and/or drain electrodes), vertically stacking devices (i.e. using thin film transistors (TFTs) or silicon on insulator (SOI) technology), using more compact transistor technology (i.e. using vertical transistor), and/or the like. For example, thin film transistors (TFTs) are transistors which are formed above the substrate within a polysilicon layer. Thin film transistors are usually stacked on top of other transistors which are formed within the substrate. This stacking achieves a high packing density. Thin film transistors (TFTs) are lithographically formed (i.e. have lithographically defined source, drain, and gate regions). Lithography limits the minimum size to which a device can be formed. Therefore, as memory arrays approach smaller cell sizes, even lithographically-defined undergated and over-gated TFTs will be too large for use within memory cells.
In order to improve density and reduce process complexity, TFTs are formed having a gate which also functions as a gate for another transistor. This method of sharing gate electrodes between two transistors allows for a reduction in the number of interconnect and gate layers and also reduces cell size. In most cases, a lithographically-defined gate which gates a planar formed transistor (i.e. a transistor formed via lithography within the substrate) functions also as a gate for an overlying TFT. Furthermore, a TFT drain of a first TFT may be used to gate a TFT channel of a second TFT and vice-versa. Once again the TFT gates are lithographically aligned/formed and are therefore no less than roughly 0.25 micron to 0.5 micron in dimensions. Lithographically-formed structures and lithographic alignment tolerances can severely limit memory cell size.
In order to further reduce the size of transistors and memory cells, vertical transistors may be used for memory cell formation. Many vertical transistors exist in the art and are usually formed by one of either trench processing or epitaxial/selective growth. Vertical transistors are in some cases difficult to form and difficult to integrate into a memory cell without using complex processing. In most cases, the formation of vertical transistors depends largely on lithography.
An improved structure is therefore required to reduce transistor top-down surface area and to reduce memory cell size.